Our vision is to transform how the world uses information to enrich life for *all*.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Key Responsibilities:
- Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of DRAM Memory array/Peripheral Logic/Analog circuits
- Actively leverage AI‑based tools, agentic workflows, and automation frameworks to:
- Accelerate schematic optimization and design‑space exploration
- Assist in parasitic analysis, sensitivity studies, and corner coverage
- Improve debug efficiency across simulation and silicon learning loops
- Define semicustom methodology for memory design
- Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments.
- Oversee and manage the layout process including floor-planning, placement, and routing
- Perform circuit-level verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools.
- Contribute to cross-group communication to work towards standardization and group success
- Drive innovation into the future memory generations and design methodology within a dynamic work environment
Minimum Qualifications
- Master’s degree in electrical or computer engineering with 4-8 years of experience in memory design.
- Solid fundamentals in CMOS circuit design, device physics and memory operation.
- Experience with SPICE-based simulation and parasitic extraction.
Preferred Qualifications
- Domain knowledge in DRAM design (DDR5, LPDDR5 or HBM or in any other memory related field)
- Domain knowledge in NAND memory design
- Exposure to or strong interest in AI/ML-assisted design flows, agentic AI or advanced automation in circuit desi