We are looking for experienced Physical Verification Engineers and Leads to join our semiconductor design team in Bangalore and Chennai.
About the Role
Key Responsibilities include performing physical verification checks, debugging and resolving violations, and collaborating with various teams to ensure timely design closure.
Responsibilities
- Perform physical verification checks, including DRC, LVS, ERC, PERC and antenna checks.
- Debug and resolve physical verification violations at block and full-chip levels.
- Work closely with Physical Design, Layout, Circuit Design and Foundry teams.
- Perform sign-off verification using industry-standard tools.
- Analyse complex layout-versus-schematic issues and provide effective solutions.
- Support tape-out activities and ensure timely design closure.
- Develop and maintain PV flows, scripts and automation.
- Review verification results and provide technical guidance to team members.
Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.
Required Skills
- Strong experience in DRC, LVS, ERC, PERC and antenna verification.
- Hands-on experience with tools such as Calibre, IC Validator or Pegasus.
- Good understanding of semiconductor layout, CMOS technology and design rules.
- Experience with advanced technology nodes is preferred.
- Knowledge of Tcl, Perl, Python or Shell scripting is an advantage.
- Solid debugging, analytical and problem-solving skills.
- Experience in block-level or full-chip physical verification.
Preferred Skills
- Experience leading Physical Verification activities for complex SoC designs.
- Ability to handle full-chip PV closure and tape-out independently.
- Experience coordinating with cross-functional and global engineering teams.
- Ability to mentor junior engineers and review technical deliverables.
Experience: 4+ Years and 8+ Years
Equal Opportunity Statement
We are committed to diversity and inclusivity in our