Typical Responsibilities
Develop and debug emulation environments using Synopsys Zebu and/or Siemens Veloce.
Port RTL designs to emulation platforms.
Integrate and debug testbenches (UVM/SystemVerilog).
Perform hardware/software co-verification.
Optimize compile and runtime performance on emulators.
Analyze functional issues and collaborate with RTL, verification, and software teams.
Required Skills
4–8 years of experience in ASIC/SoC verification or emulation.
Strong knowledge of:
SystemVerilog
UVM
Verilog/VHDL
Linux and shell scripting
Hands-on experience with:
Synopsys Zebu
Siemens Veloce
Experience with simulation tools such as VCS or Xcelium is an advantage.
Familiarity with protocols such as PCIe, USB, Ethernet, AXI, AMBA, DDR, etc., depending on the project.
Preferred Qualifications
B.E./B.Tech/M.Tech in Electronics, Electrical, or Computer Engineering.
Experience in SoC/IP verification.
Valuable debugging and communication skills.