Experience: 2 to 8 Years
Location: Bangalore
Mode Of Interview: In-Person
Role and Responsibilities 1. Block Ownership: Lead the end-to-end integration of a designated block, ensuring that the design meets functional, performance, power and area targets from specification to MTO delivery.2. SOC Flow Execution: SOC flow stack, including Spyglass-Lint, CDC analysis, Synopsys Design Compiler (DC) synthesis and VCLP (Verification-Constraint-Lint-Power) tools.3. Power-Management Expertise (Preferred): Apply UPF (Unified Power Format) knowledge to define power domains, isolation and retention strategies; this skill is considered a solid advantage.4. Cross-Team Support: Provide design-constraint assistance and technical guidance to Design Verification and Backend (Physical Design/DFT) teams, ensuring that timing, power and lint constraints are correctly applied and maintained.Skill Requirements:1. Block Integration: Proven track record of owning a complete SOC block from spec de finition through MTO sign-off.2. Design Flow Tools: Hands-on experience with Spyglass-Lint, CDC tools,
DC-Synthesis and VCLP flow.3. Power-Domain Definition: Knowledge of UPF (Unified Power Format) – preferred but not mandatory.4. Verification & Backend Collaboration: Ability to support verification and backend teams with accurate design constraints (SDC, UPF, lint rules) and troubleshooting.5. HDL Proficiency: Strong coding skills in Verilog / SystemVerilog / VHDL.6. Debugging & Analysis: Expertise in using debug tools such as Verdi or equivalent to resolve RTL and timing issues.7. Communication: Clear technical documentation (specs, constraint files, release notes) and effective cross-functional communication.Good to have:1. Analytical mindset: ability to dissect complex timing/power challenges and propose optimal solutions.2. Ownership mentality: takes responsibility for the block™s quality and schedule.3. Team player: collaborates proactively with verification, physical design, DFT and system