AT CADENCE, WE HIRE AND DEVELOP LEADERS AND INNOVATORS WHO WANT TO MAKE AN
IMPACT ON THE WORLD OF TECHNOLOGY.

* Development, automation and maintenance of EDA flows and scripts for physical
implementation
* Develop TFM to optimize PPA for IP’s and Soft Controllers
* PPA characterization and optimization of flow for performance-oriented and
power-oriented best-in-class IP cores in advanced process nodes, on TSMC,
Intel, Samsung and Rapidus Foundries
* Manage regression infrastructure that tracks quality of the RTL/flow
development as well as the PPA of the key designs.
* Digital design implementation using Cadence EDA tools - Genus, Innovus,
Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
* Develop automation scripts using AI tools and reduce design execution
turnaround time
* Required skills –
* Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed
institutes with 2 + years' experience




* Physical design experience in ASIC design workplace
* Should have knowledge of complete ASIC Design Flow, including Synthesis,
Physical Designing , Timing Analysis, Power Analysis and Formal Verification
* Prior experience in Logic Synthesis and PPA optimization techniques, Logic
Equivalence Checks ( LEC ) debug experience for production designs
* A detailed understanding of synthesis flows, hands on experience in
developing, debugging synthesis flows with EDA tools such as Genus, Fusion
Compiler.
* Should have excellent leadership, communication, analytical and problem
solving skills
* Solid scripting skills including Python and Tcl.
* Should be self-motivated and good team player.

WE’RE DOING WORK THAT MATTERS. HELP US SOLVE WHAT OTHERS CAN’T.

📌 Design Engineer II (Hyderabad)
🏢 Cadence Design Systems
📍 Hyderabad