13 Aug
|
Best NanoTech
|
Bengaluru
13 Aug
Best NanoTech
Bengaluru
Physical Design Lead Place & Route (PnR) / Static Timing Analysis (STA)
Location:
Bengaluru, India
Work Mode:
Onsite
Experience:
8 15 Years
Industry:
Semiconductor / VLSI / ASIC Design
Role Overview
We are seeking an experienced
Physical Design Lead
to drive the complete physical implementation flow for complex ASIC and SoC designs targeting advanced semiconductor technologies. The role involves leading
Place & Route (PnR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification, Power Optimization, and Signoff
while collaborating closely with RTL, DFT, Design Verification, Package, and Product Engineering teams.
The ideal candidate will have extensive experience delivering multiple successful tape-outs across advanced process nodes and possess solid leadership capabilities to mentor engineering teams and drive high-quality silicon implementation.
Key Responsibilities
- Lead complete ASIC/SoC physical design implementation from netlist through GDSII signoff.
- Drive floorplanning, power planning, placement, clock tree synthesis (CTS),
routing, optimization, and physical verification activities.
- Perform timing closure across multiple process, voltage, and temperature (PVT) corners.
- Optimize designs for Power, Performance, and Area (PPA) while meeting schedule and quality objectives.
- Conduct Static Timing Analysis (STA) and resolve setup, hold, clock skew, and signal integrity issues.
- Perform physical verification including DRC, LVS, ERC, antenna, and electromigration (EM/IR) analysis.
- Collaborate with RTL, DFT, Design Verification, Package Design, and Process Technology teams throughout the design cycle.
- Lead engineering reviews, design signoff, ECO implementation, and tape-out readiness activities.
- Develop and enhance physical design methodologies, automation flows, and reusable scripts.
- Mentor junior engineers and provide technical leadership across multiple projects.
- Support silicon bring-up and post-silicon debug w
📌 Physical Design Lead – Place (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru