Technical Manager – DFT

Location:
Bengaluru, India

Experience:
12–16 Years

About the Role

We are seeking a
Technical Manager – DFT
to lead end-to-end Design-for-Test implementation for complex SoCs. This role requires deep technical expertise in
MBIST, Scan Insertion, and ATPG
, along with the ability to mentor engineers and drive first-pass silicon success.

Key Responsibilities
- Lead DFT architecture and implementation for complex SoCs.
- Own
MBIST, Scan Insertion, ATPG, Scan Compression, and DFT Signoff
.
- Optimize fault coverage, pattern generation, and silicon debug.
- Collaborate with RTL, Physical Design, STA, Verification, and Product Engineering teams.
- Drive automation, methodology improvements, and technical excellence.
- Mentor and lead a team of DFT engineers.





Required Skills
- 12–16 years of hands-on ASIC/SoC DFT experience.
- Robust expertise in
MBIST, Scan Insertion, ATPG, Scan Compression, and Fault Coverage
.
- Experience with
Mentor Tessent, Synopsys TestMAX/DFT Compiler, or Cadence Modus
.
- Solid understanding of RTL, Physical Design, STA, Low Power (UPF), and advanced technology nodes (16nm/7nm/5nm/3nm).
- Proficiency in
TCL, Python, Perl, or Shell scripting
.

Preferred
- Experience with
LBIST, IJTAG, IEEE 1500/1149.x
, ISO 26262, and high-performance CPU, AI, Networking, or Automotive SoCs.

📌 Technical Manager – DFT (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru