Roles and Responsibilities :
- Design, develop, and verify complex digital ASICs using SystemVerilog and UVM methodologies.
- Collaborate with cross-functional teams to identify requirements and create test plans for verification of ASIC designs.
- Develop high-quality testbenches that meet functional coverage criteria and perform thorough debugging of issues found during testing.
- Participate in peer reviews to ensure adherence to coding standards, best practices, and industry guidelines.
Job Requirements :
- Hands-on experience in UVM-based testbench development and execution
- Robust understanding of sign-off flows
- Strong de-bugging skills
- Expertise in coverage analysis, including:
- Functional coverage
- Code coverage
- Experience with Gate-Level Simulation (GLS)