Full Chip Integration: Drive the full chip integration activities involving Die Architecture, Die size estimation, Floorplan and module placement to achieve optimal die are meeting all design constraints.
Power Distribution & Floorplanning: Analyze and implement full-chip power distribution strategies and floorplanning optimization to ensure efficient electrical performance, minimize parasitics, and reduce die size.
Cross-Functional Collaboration: Work closely with design and process engineering teams across multiple sites to resolve issues, align methodologies, and drive project success while maintaining high standards of accuracy and consistency.
Qualifications
15+ years of proven expertise in custom full-chip layouts across analog, digital, and mixed-signal domains, with deep understanding of power distribution and signal planning.
Floorplanning Expertise: Strong background in floorplanning strategies and placement optimization to minimize parasitics and reduce die size using a correct-by-construction approach.
Cross-Functional Collaboration: Adept at working with multi-site, cross-disciplinary teams and managing small teams to drive project success.
Communication & Methodology: Robust verbal and written communication skills with knowledge of layout automation techniques and a proactive mindset toward continuous improvement and efficiency.
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Principal VLSI Design Engineer (Bengaluru)
🏢 Western Digital
📍 Bengaluru
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