We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent 15+ years in the trenches of physical design, taking complex soft IP from RTL to something that can actually tape out without blowing timing, power, or area budgets. Timing closure is not a mystery to you, it is a discipline you have mastered across multiple nodes and multiple product cycles. You know that the difference between a design that works on paper and one that a customer can actually implement is usually found in the floorplan decisions, the clock tree strategy, and the structural choices made six months before anyone ran Fusion Compiler.
Leadership comes naturally because you have been the person others turn to when a project is stuck at 95% timing closure or when a customer calls saying they cannot meet their PPA targets. You do not just manage engineers, you coach them through the hard problems. You know how to push back on a design team when the RTL needs rework, and you know how to do it in a way that builds collaboration instead of resentment.
At Synopsys, you will lead the team responsible for ensuring our HPC controller IP is not just functionally correct but physically feasible across real customer implementations. The IP you sign off on will ship to customers building the next generation of high-performance compute systems.
What You'll Be Doing
- Lead a distributed team of physical design engineers executing multiple concurrent place-and-route projects across our HPC controller product portfolio
- Own the physical feasibility sign-off process for all HPC controller soft IP releases, defining wha