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Responsibilities:
SENIOR MANAGER SILICON DESIGN ENGINEER
The focus of this role in the AECG ASIC organization is to lead design & verification for next generation ASICs that meet Engineering, Business and Customer requirements.
THE PERSON:
You have a passion to lead high performance ASIC verification and emulation teams.
You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- SoC RTL Integration for complex digital blocks and ASIC top level to ensure high quality
- Verifying RTL implementation for complex digital blocks and ASIC top level to ensure high quality
- Develop design and verification strategies for recent features, plan volume validation and coverage strategies
- Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
- Drive coverage analysis and take necessary actions to meet coverage goals
- Integrate VIPs as needed