Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling recent possibilities.
Your Team, Your Impact
You will be part of Marvells Central CAD and Design Services (CCDS) organization the engine that powers every business unit at Marvell. Our team develops and maintains world-class design flows and infrastructure that enable Marvells semiconductor products across Data Center, Networking, Automotive, and Storage markets.
About PSI CAD team: CCDS CAD PSI team is responsible for driving Power Signal Integrity signoff methodology across Marvells worldwide business units. The team develops and maintains PSI flows within M1DP, supports design teams through tapeout, and collaborates with EDA vendors to continuously improve tool capabilities and methodology. The team operates with a "One Marvell" mindset
What You Can Expect
- Work on block-level and full-chip static IR/EM analysis flow and methodology
- Work on dynamic IR analysis methodology (vectorless and vector-based using VCD/FSDB) at block and full-chip levels, with and without package models
- Involved and tuning flows for Out-of-Context (OOC) and In-Context block-level IR analysis
- Work on Left Shifted IR Analysis like Early Rail Analysis (ERA) to detect power grid weaknesses at floorplan stage
- Interface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements.
- Develop automation scripts (Tcl, Python) to streamline IR/EM flow execution, debug, and reporting.
- Support tapeout activities by ensuring IR/EM signoff closure across blocks and full-chip designs.
- Contribute to knowledge sharing, documentation, and training of IREM CAD flows across global teams.
What Were Looking For
- B. E. /B. Tech or M. E. /M. Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field.
- 6+