Roles and Responsibilities :
- Design, develop, and execute test plans for complex digital circuits using SystemVerilog and UVM.
- Collaborate with cross-functional teams to identify requirements and create verification environments that meet customer needs.
- Develop high-quality test cases and scenarios to ensure thorough coverage of system functionality.
- Analyze results, debug issues, and provide detailed reports on test execution.
Job Requirements :
- 5-10 years of experience in hardware design verification using SystemVerilog and UVM.
- Solid understanding of digital circuit design principles and protocols (e.g., PCIe).
- Experience with one or more industry-standard simulators such as VCS, NCSIM, or ModelSim.
- Bachelor's degree in Electrical Engineering or related field.