Title: Static Timing Analysis (STA)
Location: Bengaluru
Exp: 7.5 Yrs
Roles & Responsibilities:
- Full Chip level Constraints development, validation, and timing closure
- Deep understanding of Finfet low technology node 7nm and below
- Expertise on IO budgeting, MMMC timing eco generation and convergence
- Expertise in Clock Tree analysis for deep submicron
- Hands-on experience with industry standard tools like PrimeTime, Tempus, Fishtail etc
- Deep understanding of AOCV, POCV margin methodology
- Experience in Hyperscale, ILM is advantage
- Expected to be an SME.
- Collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Mentor junior team members to enhance their skills and knowledge in timing analysis.




- Continuously evaluate and implement best practices in static timing analysis to improve team performance.

Qualified & Technical Skills:
- Must To Have Skills: Proficiency in Static Timing Analysis.
- Strong understanding of digital circuit design principles.
- Experience with timing analysis tools and methodologies.
- Ability to analyze complex timing issues and provide effective solutions.
- Familiarity with design verification processes and tools.

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📌 Static Timing Analysis (Bengaluru)
🏢 NR Consulting
📍 Bengaluru