Overview:
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Responsibilities:
THE ROLE:
The position involves working on large-scale SoC designs spanning multiple tiles, hierarchical modules, and full-chip, with a focus on low-power validation, Formal Equivalence Checking (LEC/Formality), and ECO implementation across Front-End and Physical Design netlists.
The role requires ensuring functional correctness from RTL to post-layout stages and driving closure in a fast-paced environment.
THE PERSON:
Engineer with strong fundamentals in formal verification and low-power methodologies, with a self-driven attitude, valuable analytical thinking, and effective communication skills. Should be comfortable debugging complex design issues and working across FE and PD domains.
KEY RESPONSIBILITIES:
- Perform low-power validation using UPF/CPF across RTL and Synthesis Netlist, Route, Route-PG netlist
- Debug low power issues and drive to closure for signoff
- Perform low-power validation at Hardmacro/Tile level and Full chip level
- Work on large hierarchical SoC designs involving multi-tile integration
- Ensure correctness across Front-End and Physical Design netlists
- Perform Formality / LEC checks at tile and hierarchical module level
- Verify equivalence across RTL RTL, RTL Gate, and Gate PnR
- Debug equivalence mismat
📌 Physical Design (Bengaluru)
🏢 AMD
📍 Bengaluru