Job Description
About the Job
Choosing Capgemini means choosing a place where you’ll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine what’s possible. Join us for unlocking the value of technology and drive scalable, sustainable growth.
Your Profile
In this role, you will:
Own physical implementation solutioning, methodology definition, PPA strategy, and implementation planning for complex SoCs. Serve as technical authority for physical design architecture and feasibility.
- Define implementation methodologies for large chips.
- Develop floorplanning and partitioning strategies for SoC Level.
- Drive PPA closure approach from Spec to GDS-II.
- Conduct early feasibility and QoR assessments.
- Define clocking, power, and congestion strategies.
- Guide implementation teams globally.
- TSMC Tech Node experience is must
- Experience on AI based EDA tools is required e.g. DSO or Cerberus etc.
- Review signoff readiness and implementation risks.
- Support customer technical engagements and project estimation.
Must Have
- 12+ years in Physical Design.
- Multiple tape-outs in advanced nodes (10nm and below).
- Expertise in floorplanning, CTS, timing closure, and power optimization.
- Strong knowledge of Synopsys ICC2/Fusion Compiler and/or Cadence Innovus.
- Experience with UPF and multi-voltage designs.
- Experience with large SoCs (>100M gates).
- Solid understanding of signoff methodologies.
- Should be able to support and delivery multiple projects simultaneously.
- HBM/HMC memory systems
Good to Have
- 5nm/3nm implementation experience.
- Chiplet-based floorplanning.
- 3DIC/Advanced packaging.
- HBM integration experience.
- Automotive or HPC silicon experience.
About Us
At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to lif