We are seeking a Design Verification Engineer to ensure the functional correctness of complex SoC/IP designs. You will develop testbenches, execute test plans, and drive coverage closure to ensure high-quality silicon.
Key Responsibilities
- Develop and maintain UVM-based verification environments.
- Create and execute constrained-random and directed test cases.
- Perform RTL debugging using tools like Verdi or SimVision.
- Drive Functional and Code Coverage to closure.
- Collaborate with RTL designers to resolve hardware bugs.
Required Skills
- Languages: SystemVerilog, Verilog.
- Methodology: UVM (Universal Verification Methodology).
- Protocols: Knowledge of AMBA (AXI/AHB), PCIe, or DDR.
- Tools: Experience with simulators (Synopsys VCS, Cadence Xcelium, or Questa).
- Scripting: Python, Perl, or Shell.
Education
- B.E./B.Tech or M.Tech in Electronics, VLSI, or Electrical Engineering.
Note - Candidates are expected to join between 0 - 15 days.