sensAI team at Lattice Semiconductor, innovates and creates solutions to enable edgeAI with programmable low power devices. Our vision is to unleash FPGA to add intelligence to every sensor used in Automotive, industrial and consumer products. As a senior member of the team, you will be responsible for developing and enhancing machine learning engine that infers neural networks on resource constrained devices. You need to bring expertise in machine learning to enable computer vision, robotics, human-machine interaction, or other related domains.
Job Description
We are seeking a highly motivated Senior Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine. You are responsible to implement ML operators efficiently using resources on low power FPGA. You need to bring experience in optimizing data path for high throughput and low latency. Valuable understanding of neural network accelerators and/or DSP processors is essential to be successful in this job.
Requirements
Key Skills
- In-depth experience in designing and developing RTL using Verilog, System Verilog-HDL
- Ability to carry out functional simulation using industry standard simulation tools such as Xcelium-Cadence, VCS-Synopsys
- Architect and design RTL for Machine Learning compute engines targeting low power FPGA platforms
- Collaborate with algorithm and architecture teams to translate ML models/operators into efficient hardware micro architectures
- Experience in image processing and DSP algorithms implementation
- Deep understanding of machine learning, data models to optimally map it with hardware
- Experience in FPGA/ASIC synthesis flow, timing closure
- Working knowledge of computer architecture and memory management
- Experience with C and/or SystemC is a plus
Education and General:
- BE/MTech/PhD in Electronics, Electrical or Computer Engineering
- Minimum of 14 years (12 years for MTech and 8 years for PHD) experience in R
📌 Sr. Staff RTL Eng (Pune)
🏢 Lattice Semiconductor (india)
📍 Pune
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