Principal Engineer, STA (Bengaluru)

Principal Engineer, STA (Bengaluru)

13 Aug
|
Astera Labs
|
Bengaluru

13 Aug

Astera Labs

Bengaluru

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, versatile systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview
Astera Labs is hiring a
Principal Engineer, Static Timing Analysis
to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes,



partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.

This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on — and you'll have the ownership, influence, and tooling to do the best work of your career.

Key Responsibilities
- Full-Chip STA Signoff & Timing Closure
- Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
- Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from early floorplan through tapeout
- Analyze and resolve setup, hold, recovery/removal, and clock-domain crossing (CDC) timing violations at the chip level
- Methodology & Flow Development
- Define and evolv

📌 Principal Engineer, STA (Bengaluru)
🏢 Astera Labs
📍 Bengaluru

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