Participate in the functional verification using SystemVerilog, UVM, and Perl. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules,
and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.
EXPERIENCE AND EDUCATION:
3-6 years
of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
Experience in Verilog/SystemVerilog/SystemC, preferred;
Memory protocol DDR5, LP5, and LP6 knowledge is desirable
Experience in C/Verilog workplace using DPI/PLI, preferred;