Lattice Semiconductor | Full time | Onsite | Pune / Hyderabad, India
The Role
FPGA memory isn't commodity memory. Every SRAM and configuration RAM block in a Lattice device is custom-designed — bitcell to periphery, architecture to timing model — tuned for the most demanding power, performance, and area targets in programmable logic.
If this is the kind of work you've been doing, you already know how rare it is. So do we.
What You'll Own
- Design and develop custom high-speed, low-power SRAM and FPGA configuration RAM (CRAM) — bitcell, sense amplifiers, read/write circuits, wordline drivers, and periphery
- Define memory architectures in advanced semiconductor technologies — FinFET and nanometer CMOS
- Own the full embedded memory design flow: architecture → circuit design → physical implementation → compiler usage → characterization → timing → model generation
- Perform schematic capture, simulation, and margin verification across major memory blocks
- Drive layout planning — tight pitch-matched memory layout is core to this role
- Define and deliver memory PPA (Performance, Power, Area) and yield targets in close collaboration with architecture and design teams
- Apply variation-aware design techniques to ensure robust operation across process corners
- Bring innovative ideas that influence memory design across Lattice's FPGA product portfolio
The Work That Qualifies You
We're filtering by what you've actually done:
- You've owned SRAM bitcell and periphery design — not just integrated someone else's compiler
- You've characterized memory margins and understand what process variation does to yield
- You've driven the full memory flow end-to-end — from architecture decisions through to timing models
- You've designed in FinFET or sub-20nm CMOS and understand the tradeoffs at advanced nodes
- You've worked on FPGA configuration memory (CRAM) — rare, and a genuine differentiator here
- You've collaborated with a