We are looking for experienced
DFT Engineers
to join an exciting
ASIC Controller
project. If you have strong hands-on experience in
Scan Insertion
and
ATPG
, we'd love to connect with you

Key Skills:

✅ Scan Insertion & Scan Stitching

✅ ATPG (Automatic Test Pattern Generation)

✅ Robust understanding of DFT concepts and methodologies

✅ Knowledge of JTAG / Boundary Scan concepts

✅ Exposure to memory-based system architectures

✅ Experience with industry-standard DFT tools (Cadence/Synopsys preferred)

✅ Familiarity with Synopsys Design Compiler (DC) is an added advantage

Role Highlights:

• Perform DFT implementation for ASIC controller designs

• Execute gate-level structural testing activities

• Collaborate with RTL/Design teams to improve testability

• Work with standard DFT toolchains for implementation and validation

Education:

? Bachelor's or Master's degree in Electronics, Electrical, Computer Engineering, or a related field.

Note:

✔️ This role focuses on
gate-level structural testing
.

✔️ Memory BIST/RAM BIST experience is
not mandatory
.

✔️ Experience with TSMC technology nodes is preferred.

3-6 Years experience

📌 DFT Engineer (Hyderabad)
🏢 pozibility technologies
📍 Hyderabad