Staff Physical Design Engineer (Pune)

Staff Physical Design Engineer (Pune)

13 Aug
|
Lattice Semiconductor (india)
|
Pune

13 Aug

Lattice Semiconductor (india)

Pune

About the Role

Lattice Semiconductor is seeking a Staff Physical Design Engineer to join our Pune engineering center. In this role, you will own physical implementation of complex digital blocks and IP for our low-power FPGA products from netlist to GDSII working closely with RTL design, integration, and architecture teams to deliver first-pass silicon.

Responsibilities
- Own block-level physical design execution: floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure
- Drive synthesis and place-and-route flows using industry-standard EDA tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, or equivalent)
- Perform static timing analysis and closure across PVT corners and modes
- Execute physical verification and sign-off: DRC, LVS, ERC, antenna, EM/IR analysis
- Implement low-power design techniques UPF-based power intent, power gating, multi-Vt optimization
- Collaborate with RTL, DFT, and integration teams to resolve design convergence issues and support ECO cycles




- Contribute to flow automation and methodology improvements using scripting (TCL, Python, Perl)
- Support tape-out activities and correlate physical design metrics with post-silicon results

Requirements
- Bachelors or Masters degree in Electronics/Electrical Engineering or related field
- 6+ years of hands-on physical design experience in ASIC/SoC or FPGA silicon development
- Robust expertise in synthesis, PR, STA, and physical sign-off on advanced process nodes
- Working knowledge of low-power implementation (UPF/CPF) and design convergence at block and subsystem level
- Proficiency in TCL/Python scripting for flow automation
- Strong debugging skills and a track record of successful tape-outs
- Excellent cross-functional communication and ownership mindset

Preferred
- Experience with FPGA or custom silicon physical implementation
- Exposure to EM/IR analysis tools (Ansys RedHawk/Totem) and DFM closure
- Advanced node experience (16nm and below)

Disclaim

📌 Staff Physical Design Engineer (Pune)
🏢 Lattice Semiconductor (india)
📍 Pune

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