Meet the Team
Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world
Your Impact
Our creative and talented Physical Design team in Bangalore, India. As a member of this team, you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
Minimum Qualifications
- ### Bachelor's or a Master’s Degree in Electrical or Computer Engineering with 5+ years of expereince is required.
- ### All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- ### Hierarchical design implementation approach, Timing closure, physical convergence.
- ### Power Integrity Analysis
- ### Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
Preferred Qualifications
- ### Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
- ### Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
- ### Positive understanding of different CTS strategies and pro