Design and Verification Engineer (Bengaluru)

Design and Verification Engineer (Bengaluru)

13 Aug
|
Shervani Tech Hub
|
Bengaluru

13 Aug

Shervani Tech Hub

Bengaluru

Robust experience in SystemVerilog and UVM

Solid understanding of SoC/IP verification methodologies

Good debugging and problem-solving skills

Develop and execute verification plans using SystemVerilog/UVM

Perform functional verification of SoC/IP components

Debug failures across simulation, emulation, and silicon

Work closely with design and DFT teams for testability and coverage

Analyze and validate test patterns (ATPG/ATE)

Support post-silicon validation and bring-up

📌 Design and Verification Engineer (Bengaluru)
🏢 Shervani Tech Hub
📍 Bengaluru

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