Location: Bangalore
Experience: 10+ Years
Notice period: Immediate
JD for Lead RTL Integration:
10+ years of experience in RTL Design, SoC Integration, or ASIC Development.
Robust hands-on experience in RTL/SoC Integration.
Experience with DDR4/DDR5/LPDDR and PCIe Gen3/Gen4/Gen5 integration.
Experience with ARM or RISC-V processor subsystems.
Strong knowledge of Verilog/System Verilog.
Experience with AXI/AHB/APB protocols and interconnect architectures.
Understanding of clocking, reset architecture, CDC, RDC, and low-power methodologies.
Experience in IP integration, subsystem integration, and SoC-level debugging.
Familiarity with Lint, CDC, synthesis, and STA flows.
Scripting experience in Python, Perl, Tcl, or Shell.