Join the hardware engineering team building the next generation of custom silicon that powers breakthrough AI/ML models and hyperscale cloud services. In this role, you will leverage your digital verification expertise to validate complex TPU microarchitectures, ensuring zero-bug functionality before tape-out.
Key Responsibilities
- Verification Planning:
Collaborate with microarchitecture and design teams to understand specifications and define comprehensive test plans targeting critical operational and corner-case scenarios.
- Testbench Development:
Architect, build, and maintain scalable, constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
- Coverage Analysis:
Define, track, and close functional and code coverage metrics to identify verification holes and guarantee rigorous testing.
- Debugging & Problem Solving:
Work closely with design engineers to debug failing tests, root-cause RTL bugs, and iterate on test cases.
- Methodology Innovation:
Optimize verification flows, build regression systems,
and develop automation scripts (e.g., Python or Perl) to increase verification throughput and efficiency.
Qualifications
- Education:
Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience.
- Experience:
5+ years of experience verifying digital logic at the RTL level for ASICs or FPGAs.
- Methodologies:
Deep expertise in industry-standard verification methodologies including SystemVerilog and UVM.
- Workplace Tools:
Experience with industry-standard simulators (e.g., Synopsys VCS, Cadence Xcelium) and regression systems.
Preferred Qualifications
- Education:
Master’s degree or PhD in Electrical Engineering or Computer Science, with a heavy emphasis on computer architecture.
- Domain Knowledge:
Direct experience verifying AI/ML Accelerators, GPUs, or highly parallel vector processing units.
- Advanced Debugging:
Familiarity w
📌 P Design Verification Engineer (Bengaluru)
🏢 Qpisemi
📍 Bengaluru
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