Experience: 11+ Years (Advanced Node Experience Preferred)

We are looking for an experienced
Full-Chip Physical Design Engineer
with solid expertise in advanced-node SoC implementation and signoff to join our growing semiconductor team.

Key Responsibilities:
- Hands-on experience with
AMD Tile Builder Flow
for block and full-chip implementations.
- Own the complete
RTL-to-GDSII
implementation flow including Synthesis, Floorplanning, Place & Route, STA, EMIR, ECO, and Signoff.
- Drive
Full-Chip Floorplanning
, partitioning, macro/IO placement, power planning, and hierarchical integration.
- Perform
Full-Chip Timing Closure
, MCMM analysis, path-based analysis (PBA), timing signoff, and ECO closure.
- Develop, validate, and debug
SDC constraints
for Functional, DFT, and Low-Power modes.
- Implement
UPF-based Low-Power Designs
with power domains, isolation, level shifters, retention, and power switches.




- Resolve complex implementation challenges involving timing, congestion, DRC, EMIR, power, and reliability.
- Collaborate closely with RTL, DFT, Architecture, Physical Design, and Signoff teams.
- Take ownership of
Full-Chip Integration and Signoff
.

Required Skills:

✅ AMD Tile Builder Flow

✅ RTL-to-GDSII Implementation

✅ Full-Chip Physical Design & Integration

✅ Timing Closure (MCMM, PBA, ECO)

✅ SDC Constraint Development & Debugging

✅ UPF / Low-Power Design Implementation

✅ Advanced Technology Nodes:
TSMC N6 / N5 / N4 / N3 / N2P

✅ Tools:
Fusion Compiler, PrimeTime, Calibre, RedHawk-SC

✅ Experience with large hierarchical SoCs and multi-voltage, multi-power-domain designs

📌 Full-Chip Physical Design Engineer (Bengaluru)
🏢 pozibility technologies
📍 Bengaluru