•Design & code digital RTL blocks in Verilog / System Verilog per specification
•Run synthesis using Synopsys Design Compiler or Cadence Genus & meet PPA targets
•Perform CDC, RDC checks; resolve multi-clock domain issues
•Work with UVM verification
Required Candidate profile
3 - 7 yrs
Exp in Verilog/SystemVerilog, Static Timing Analysis(STA),Tcl scripting
RTL microarchitecture design,CDC/RDC analysis, Git /version control, Synopsys DC or Cadence Genus Work on SoC projects