A VLSI Physical Design Engineer is responsible for converting a circuit (netlist) into a manufacturable chip layout while meeting performance, power, and area (PPA) targets.
Here’s a transparent, industry-style job description (JD) you can use:
Job Title: Physical Design Engineer (VLSI)
Job Overview
Responsible for end-to-end physical design implementation of ASIC/SoC blocks from synthesis to GDSII, ensuring timing closure, signal integrity, and manufacturability.
Key Responsibilities
1. Floorplanning
Define chip/block size, aspect ratio
Macro placement (SRAM, IP blocks)
Power planning (VDD/VSS grids, rings)
2. Placement
Standard cell placement
Optimize for timing, congestion, and power
3. Clock Tree Synthesis (CTS)
Build clock tree for low skew and latency
Handle clock gating and balancing
4. Routing
Global and detailed routing
Fix congestion, DRC violations
5. Timing Closure
Setup & hold fixing
Use STA tools (timing analysis)
Buffer insertion, cell sizing
6. Physical Verification
DRC (Design Rule Check)
LVS (Layout vs Schematic)
Antenna and ERC checks
7.
Sign-off Checks
IR drop analysis
Electromigration (EM) checks
Parasitic extraction (RC extraction)
8. ECO Implementation
Engineering Change Orders for last-minute fixes
Required Skills
Technical Skills
Good understanding of:
CMOS fundamentals
Timing concepts (setup, hold, skew)
RC parasitics
Tools knowledge:
Cadence (Innovus)
Synopsys (ICC2, PrimeTime)
Scripting:
TCL (must-have)
Basic Unix/Linux commands
Preferred Skills
Low power design techniques
Multi-voltage domain handling
Experience in advanced nodes (7nm, 5nm, etc.)
Educational Qualification
B.E / B.Tech / M.Tech in Electronics / VLSI / ECE
Experience Levels
0–2 Years (Fresher/Junior)
Basic PD flow understanding
Assist in placement, routing, DRC fixing,Aligo ,Alt Tm