Hi All,
Greetings from Eximietas Design...
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We're Hiring | Senior DFT Lead | Eximietas Design | Visakhapatnam Location.
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Locations:
- India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
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San Jose (Bay Area), USA
- Eligibility (USA):
U.S. Permanent Residents (Green Card holders).
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Experience:
5 to 20+ Years
Job Description:
We are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.
Key Skills:
✔ End-to-End DFT Flow Ownership.
✔ Scan Insertion, EDT & OCC.
✔ ATPG, DRC Analysis & Coverage Closure.
✔ Pattern Simulation & Debugging.
✔ SoC Integration & Pattern Retargeting.
✔ MBIST, IJTAG & JTAG Implementation.
✔ DFT Sign-off Activities.
Tools Expertise:
? Siemens Tessent.
? Synopsys TestMAX / TetraMAX.
? Cadence Modus.
Preferred Skills:
✅ Streaming Scan Network (SSN).
✅ Analog & Mixed-Signal DFT.
✅ SpyGlass DFT.
✅ RTL DFT Methodologies.
✅ TCL, Python & Perl Scripting.
Core Responsibilities:
• End-to-end ownership of DFT implementation flow from RTL to sign-off.
• Scan architecture implementation including EDT & OCC.
• ATPG, DRC analysis, coverage optimization, and pattern simulations.
• SoC integration, pattern retargeting, and DFT debugging.
• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
• Collaboration with Design, Verification, and Physical Design teams.
• DFT sign-off ownership and deliverables.
Technical Requirements:
• Strong experience in ATPG simulations and netlist handling.
• Expertise in block-level and SoC-level pattern retargeting/debugging.
• Solid understanding of ICL and PDL standards.
• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.
? Interested candidates can share their updated resume at:
[email protected]
? Contact:
+91 (phone hidden)
? Referrals are highly appreciated. Please share within your network.
Best
📌 DFT Lead_Eximietas Design_Vizag (Visakhapatnam)
🏢 Eximietas Design
📍 Visakhapatnam