We are hiring Design verification Engineers PCIe Design IP R & D Team at Bangalore.
Skills: Robust Experience in SV/UVM/Test bench development, working knowledge of PCIe / CXL Protocol
Experience : 5+ yrs
Notice period: Immediate to 60 days
Salary : Best in Industry
Key Responsibilities
Lead end to end IP verification activities
Develop detail test plans and verification strategies
Build and maintain UVM based test benches using system verilog
Knowledge of protocols (AXI/ AHB/APB) and PCIe is must