Looking for AMS Layout Engineers with 3–5 years of experience in analog and mixed-signal layout design.
Candidate should have strong understanding of VLSI fundamentals, layout methodologies, and physical design from floorplan to closure. Hands-on experience in AMS blocks and good knowledge of layout effects and reliability concepts is required.
Robust debugging skills, automation interest, and ability to work in collaborative environments are expected.

Requirements
Strong knowledge of VLSI concepts: CMOS, IC fabrication, FinFET, RC networks.
Experience in AMS, Digital, IO, Standard Cell, and Memory layouts from floorplan to closure.
Hands-on experience in AMS blocks such as PLL, RX, TX, Data Converters, Regulators, and Custom Cells.




Understanding of reliability concepts: EM/IR, ESD, and Latch-up.
Knowledge of layout effects related to parasitics, speed, power, and area.
Good debugging skills with strong physical verification understanding.
Scripting knowledge (TCL, Perl, Python) is a plus.
Good communication skills and flexibility to work at client/ODC locations.
Qualifications & Experience
Education: BE/B.Tech/M.Sc. (ECE/EEE) or M.Tech VLSI
Experience: 3–5 Years

Benefits
As per SignOff Policy

📌 Design Engineer II (Hyderabad)
🏢 SIGNOFF SEMICONDUCTORS
📍 Hyderabad