- Top 3 skills: "More than 3 years of experience in PDN/EMIR closure in digital ASIC chips.
- Own SoC level IR drop, Signal and power EM sign-off
- Identify issues causing high EMIR, debug and optimal provide solutions
Key Responsibilities:
- Own SoC level IR drop, Signal and power EM sign-off
- Identify issues causing high EMIR, debug and optimal provide solutions.
- Closely co-work with physical design team, to drive IREM closure
Preferred Experience:
- More than 3 years of experience in PDN/EMIR closure in digital ASIC chips. Preferred 8+ years or more years of experienc
- Knowledgeable in physical design flow and impact of different aspects of designs causing IR EM issues
- Expert in usage of Redhawk tools for static/Dynamic analysis using vectorless/vector approach and PG EM and Signal EM analysis,
- Involved in Tape-in of multiple SoCs