Position Description:

- Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
- Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level)
- Active participation in post silicon validation, correlation and test activities using in-house test and validation lab
- Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change
- Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow
- Perform custom RF Physical Design, including block-level and top level layouts, floorplanning, package routing




- Supports complex projects or leads smaller independent design activities
- Support CAD and drawing updates on both sustaining/recent project with minimal supervision
- Contributes to PD architecture/Plug-In Unit at the unit level

Position Requirements:

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent with VLSI experience as a Physical design engineer, with a large portion of the recent work experience on RTL design and development.
- Motivation for layout automation, methodology development, SOC layout views and data conversion is desired
- Versatility with scripts to automate design flow
- 5 -10 + years of experience in large VLSI physical design implementation and have experience with ICC Innovus tool and must have worked on less than 7nm technology.
- Successful track record of delivering designs to production is a must
- Should be a power user of P&R; and timing analysis CAD tools from Synopsys (ICC/DC/PT/STAR-RC/ICV), Cadence (First Encounter/Innovus/Voltus), Mentor ( Olympus )
- Full design cycle from RTL to GDSII

📌 VLSI Physical Design Engineer (Hyderabad)
🏢 Bay Area Technology Solutions
📍 Hyderabad