Roles and Responsibilities :

- Develop and implement verification test plans and create directed and randomized test cases.
- Implement scoreboards, checkers, and bus functional models within UVM environments.
- Troubleshoot issues during the development process using debugging techniques and collaboration.
- Analyze logs and develop high-quality code coverage metrics.
- Collaborate with cross-functional teams to identify requirements and develop test plans.
- Work on AMBA-based designs such as AXI and CHI.

Job Requirements :

- 10+ Years of experience in developing verification test plans and creating directed and randomized test cases.
- Experience in implementing scoreboards, checkers, and bus functional models within UVM environments.
- Proficiency in System Verilog assertions and UVM methodology.
- Team-oriented and able to prioritize team success over individual results.
- High attention to detail and commitment to quality.
- Solid focus on meeting project deadlines and deliverables.
- Experience with Cadence or Synopsys verification suites is preferred.
- Proficient in English with strong communication skills.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Ericsson
📍 Bengaluru