- Experience or solid interest in developing memory compilers, addressing layout-related issues, and ensuring optimization.
- Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout.
- Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
- Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area.
- Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL.
- Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery Excellent communication skills and proactive at work.
- Excellent communication skills and proactive at work