Job DescriptionSTA Design Engineer
nWe need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality.
nSkills:
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- Overall 3+ years industry experience in Backend (Physical Design) STA at SoC level.n
- Hands-on experience with Timing constraints authoring, managing complex clocking, reset, and design hierarchy.n
- Proven experience in minimum 2 Tape-out sign offs.n
- Knowledge of IP and SoC design flows and methodologiesn
- Ability to work with local and remote teams (Architecture, RTL, DFT, and Physical Design)n
- Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys)n
- Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.n
- Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skillsn

nTraits:
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- Adaptable, Adaptable, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.n
- Solutions orientation; Quality driven; Execution mindedn

📌 Static Timing Analysis (Hyderabad)
🏢 Sevya Multimedia
📍 Hyderabad