You are seeking a NoC / Interconnect Verification Engineer with at least 9 years of experience, particularly in ARM CMN or cache-coherent fabric architectures. Your role will involve verifying on-chip interconnects, coherency flows, packet routing, and data ordering at subsystem and SoC levels.- Develop SystemVerilog/UVM-based verification environments for CMN or custom NoC fabrics- Verify traffic routing, arbitration, QoS, deadlock/livelock scenarios, and coherency flows- Create stimulus/monitors for AXI, ACE, CHI, CCIX, or CXL protocols- Debug ordering violations, congestion, and coherency race conditions- Collaborate with RTL, performance, and architecture teams for coverage sign-offTo qualify for this role, you should have:- 5 years of experience in SoC / Interconnect / Fabric verification- Hands-on expertise with ARM CMN, NOC, or similar cache-coherent interconnect IPs- Strong background in AXI, ACE, CHI, CCIX, or CXL protocol verification- Solid command of SystemVerilog, UVM, and coverage-driven verification methodologies- Scripting proficiency (Python / Perl / Tcl) for automationPreferred qualifications include experience analyzing NoC latency, bandwidth, and congestion performance, as well as familiarity with power/performance modeling or formal verification for NoC fabrics.If interested, you can contact Uday at Mulya Technologies via email:



View email address on easyhiring.pro You are seeking a NoC / Interconnect Verification Engineer with at least 9 years of experience, particularly in ARM CMN or cache-coherent fabric architectures. Your role will involve verifying on-chip interconnects, coherency flows, packet routing, and data ordering at subsystem and SoC levels.- Develop SystemVerilog/UVM-based verification environments for CMN or custom NoC fabrics- Verify traffic routing, arbitration, QoS, deadlock/livelock scenarios, and coherency flows- Create stimulus/monitors for AXI, ACE, CHI, CCIX, or CXL protocols- Debug ordering violations, congestion, and coherency race conditions- Collaborate with RTL, performance, and architecture teams for coverage sign-offTo qualify for this role, you should have:- 5 years of experience in SoC / Interconnect / Fabric verification- Hands-on expertise with ARM CMN, NOC, or similar cache-coherent interconnect IPs- Solid background in AXI, ACE, CHI, CCIX, or CXL protocol verification- Solid command of SystemVerilog, UVM, and coverage-driven verification methodologies- Scripting proficiency (Python / Perl / Tcl) for automationPreferred qualifications include experience analyzing NoC latency, bandwidth, and congestion performance, as well as familiarity with power/performance modeling or formal verification for NoC fabrics.If interested, you can contact Uday at Mulya Technologies via email: View email address on easyhiring.pro

📌 Lead NoC / CMN Verification Engineer (Chennai)
🏢 Important Business
📍 Chennai