We are looking for a highly skilled & experienced PD expert to join our Advanced SOCs and MCUs Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions
Scope of Responsibilities:
- As part of the Design Enablement team of the organization, you need to work closely with cross functional teams to develop and define Physical Design methodology to meet advanced SOCs and MCUs and IP level objectives on all geometry nodes (3/5/16/22nm)
- Your scope of work will cover tools and flows definition, requirement management for Place & Route, UPF, Formal Verification, Floorplan & Power-Plan
- You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies.
- Work with EDA Vendors to review and resolve blocking issues
- You will be an actor of change for deploying recent tools & methodologies across the organization
Specific skills & knowledge :
- 6-10 years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route
- Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence
- Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project
- Experience in customizing flows & methodology to meet low power & area objectives of SoCs/MCUs
- Strong scripting skills for Automation and Flow development using PERL/TCL/Py