Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Key Responsibilities:
- Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development.
- Define and review module interfaces and system-level architecture.
- Actively leverage AI‑based tools, agentic workflows, and automation frameworks to:
- Accelerate RTL design optimization and design‑space exploration
- Assist in testbench generation and corner coverage
- Improve debug efficiency across simulation and silicon learning loops
- Define semicustom methodology for memory design
- Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis.
- Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification,
and design sign‑off environments.
- Collaborate closely with architecture, design, verification, and physical design / layout teams.
- Oversee and manage the layout process including floor-planning, placement, and routing.
- Perform block-level and full-chip verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools.
- Contribute to cross-group communication to work towards standardization and group success
- Provide technical mentorship and participate in design and methodology reviews.
- Drive innovation into the future memory generations and design methodology within a dynamic work workplace
Minimum Qualifications
- Master’s degree in electrical or computer engineering with 6-10 years of experience in RTL design.
- Solid knowledge of asynchronous and synchronous design concepts and CDC methodologies.
- Deep understanding of SoC