Job Description:
Key Responsibilities:
Leadership and Management:
-Manage and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation.
-Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high-quality delivery.
DFT Design and Verification:
-Implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using industry-standard tools.
-Drive DFT verification for features such as scan, arrays, and DFD using RTL simulations and emulation.
-Create plans and tests for validating portions of complex microarchitecture using written specs, RTL code, and other test guides.
Technical Problem Solving:
-Debug failures to root cause and learn architecture/microarchitecture deeply.
-Collaborate with post-silicon/manufacturing teams on ATE, debugging and resolving issues.
-Cross-Functional Collaboration:
-Work closely with global stakeholders to address DFT challenges and improve product quality.
-Ensure alignment of timelines and deliverables across sites.
Qualifications:
• 10+ years of experience in DFT domain at IP or SoC level.
• 5+ years of experience managing and leading teams.
• Robust knowledge and experience in Spyglass DFT.
• Hands-on skills in implementing JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry.
• Expertise in DFT Design and verification using RTL simulations and emulation.
• Good understanding of timing constraints and DFT mode timing analysis.
• Proficiency in RTL coding and shell scripting.
• Experience working with post-silicon/manufacturing teams on ATE, including debugging and issue resolution.
• Experience with X86 CPU architecture and microarchitecture.
• Familiarity with advanced process nodes and hierarchical DFT strategies.
• Strong communication and leadership skills for cross-site collaboration.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
Silicon and Plat
📌 CPU DFT Manager (Bengaluru)
🏢 Intel
📍 Bengaluru
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