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Job Description: We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include
- STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi voltage domain designs. Timing analysis, and timing closure at Partition/Sub-system/FC level.
- Driving Convergence by influencing APR, Design teams stakeholders
- Familiar with Constraint development and clean up.




- Valuable understanding of different CTS strategies and providing the feedback to Implementation Team.
- Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Prime Time based ECO flows.
- Work on Automation scripts with in STA tools for Methodology development.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Familiar with digital design Implementation RTL to GDSII : Synopsys/Cadence tools.
- Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics especially 28nm and below technology nodes.
- Handson experience on timing closure industry standard high speed interfaces like DDR, PCIE, HBM, D2D

Qualification :
- 12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic

📌 Principal STA Engineer (Bengaluru)
🏢 Analog Devices
📍 Bengaluru