We are seeking an experienced Physical Design Engineer to join our team developing next-generation AI acceleration SoCs and chiplets at EdgeCortix. In this role, you will play a key part in driving synthesis, timing closure, and design optimization in close collaboration with our RTL, architecture, and external implementation partners. This is an exciting opportunity to contribute to cutting-edge silicon development that powers advanced AI systems at the edge.
The Team
As a team, we are working to define and solve the hardest problems in AI including computer vision, speech, and natural language, geared towards real-time capabilities on small to medium-form factor devices. We originated out of multiple years of research, as such at our core we value learning, intellectual curiosity, and self-starters. We have the ambitious goal of enabling cloud-level performance with significantly better energy efficiency for AI inference at the edge.
About EdgeCortix
EdgeCortix is a deep-tech,
fabless semiconductor startup revolutionizing edge computing with artificial intelligence and high-efficiency system-on-chip (SoC) design. Founded on years of advanced research, our proprietary hardware-software co-design methodology and Agile Neural Accelerator® AI processor IP are reshaping the AI hardware space. Headquartered in Tokyo, Japan, we also operate in Singapore, the United States (California and Virginia), and India.
Your Role and Responsibilities
As a Physical Design Engineer, you will contribute to the implementation of our next-generation AI acceleration SoCs and chiplets. As part of small internal PD team, you will be responsible for driving key aspects of the front-end synthesis experiments to determine optimal PPA operating point and taking the IPs through Place and Route flow through close collaboration with RTL design and architecture teams. The sign-off activities and regular P&R; progress has to be closely collaborated with our external implementat