Staff Engineer, Design Verification (Bengaluru)

Staff Engineer, Design Verification (Bengaluru)

13 Aug
|
renesas electronics
|
Bengaluru

13 Aug

renesas electronics

Bengaluru

Company Description

Responsibilities:
- Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
- Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
- Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
- Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with transparent metrics
- Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
- Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
- Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
- Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
- Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors




- Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
- Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
- Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
- Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

Qualifications
- Bachelor’s or Master’s degree in electronics Engineering
- 5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
- Strong expertise in UVM‑based testbench architecture and development
- Proven experience in metric‑driven verification, including functional and code coverage closure
- Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
- Experience with directed and constrained‑random verifi

📌 Staff Engineer, Design Verification (Bengaluru)
🏢 renesas electronics
📍 Bengaluru

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