ASIC Design Engineer
This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for valuable. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
What You'll Do
- Define and architect high-performance blocks for next-generation networking ASICs.
- Perform micro-architecture and RTL logic design to maximize throughput while optimizing power efficiency.
- Partner with the verification team to develop test plans and debug functional issues.
- Collaborate with the physical design team to define timing constraints, analyze timing violations, and implement timing closure solutions.
What You Need to Bring
- Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
- 8+ years of experience in VLSI/ASIC design.
- Strong expertise in Verilog RTL coding.
- Working knowledge of Synopsys Design Compiler, Verplex LEC, and SpyGlass (preferred).
- Experience designing networking ASICs for protocols such as Ethernet and FCoE is an advantage.
- Knowledge of high-performance memory subsystem design.
- Understanding of multi-clock domain synchronization and high-speed serial interfaces.
- Strong analytical, problem-solving, and ASIC debugging skills.
- Excellent written and verbal communication skills.
Additional Skills:
Accountability, Accountability, Action Planning, Active