Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Role Overview
We are seeking an experienced RTL Design Engineer with 5–15 years of hands-on experience in digital design and IP development. The ideal candidate will have strong expertise in RTL architecture and micro-architecture definition, with experience developing reusable IP for SoC integration.
Exposure to wireless systems (preferably Wi-Fi) and communication/peripheral IP such as SPI, UART, I2C, DMA, etc., is highly desirable.

Key Responsibilities
- Develop high-quality,



synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
- Drive IP development from specification to tape-out.
- Ensure designs meet performance, power, and area (PPA) targets.
- Develop and maintain design documentation (micro-architecture spec, design spec, integration guide).
- Collaborate with verification teams to develop test plans and debug functional issues.
- Support synthesis, lint, CDC/RDC, and timing closure activities.
- Work closely with SoC integration teams for IP integration and bring-up.
- Support post-silicon validation and debug.
- Contribute to IP reuse, configurability, and design methodology improvements.
- Mentor junior engineers

Required Qualifications
- Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
- 5–15 years of experience in RTL design and digital IP development.
- Solid proficiency in Verilog/SystemVerilog.
- Solid understandin

📌 Staff Engineer (Hyderabad)
🏢 Silicon Laboratories
📍 Hyderabad