SOC Design Verification:
Job-responsibilities:
• Owning Complete SOC Level Verification of Mid & Volume Segment Exynos SOCs.
• Collaborating/Owning SOC Level verification with Korea team for various SOCs based on Exynos platform – Mobile (Flagship), Automotive, Custom SOCs
• Team’s ownership – Equivalent to 3 complete SOC ownership across all Segments.
• Working on all aspects of SOC Verification – CPU-SS, BUS, Multimedia, Clock & Power, High Speed Interfaces, DDR, GPU, AI & ML accelerators.
• Owning performance verification and system verification activities and working on Performance estimation & virtual prototyping activities
Graphics Verification Engineer
Job-responsibilities:
• Develop/demonstrate a solid understanding of the Graphics Pipeline.
• Review architecture and micro-architecture specifications.
• Work closely with Architects and Logic Designers.
• Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and Assertion Plans needed to target zero defect post-silicon quality.
• Develop scalable Test benches in System Verilog and UVM.
• Integrate C++ Reference Models into Scoreboards via System Verilog DPI.
• Develop Tests, Functional Coverage Models and System Verilog Assertions.
• Root cause regression failures by debugging Tests/Sequences, RTL and C++ Models.
• Maintain higher regression efficiency via Test/Coverage Grading, Compute Farm and Disk utilization, etc.
• Drive Code and Functional Coverage closure.
• Support debug of Unit RTL/Checkers at higher levels of integration such as Subsystem/Top.
• Solid understanding of Computer Architecture.
• Knowledge of GPU and Graphics pipelines.
• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
• Strong functional verification experience including Test planning, Test bench Architecture, Test/Coverage Model/Assertion Development.
• Strong debugging skills.
• Strong programming skills with positive understanding of algorithms and data structure