Responsibilities:
- Lead, supervise, mentor, and develop a team of verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects. (20%)
- Track & report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early. Report to remote verification & design teams. Coordinate with project management and cross-functional teams. (20%)
- Drive definition and implementation of comprehensive verification plans and test strategies for digital/mixed-signal integrated circuit designs. Work closely with design teams to understand micro-architecture and functional specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (20%)
- Manage design and implementation of complex testbenches using System Verilog and UVM methodology.
Lead block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Improve verification scalability and portability from project to project by workplace enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (20%)
- Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)
- Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
- Technical support to silicon lab evaluation, test, product and application engineers. (5%)
Minimum Qualifications:
- 8+ years of industry experience in integrated circuit design verification (DV)
- 3+ years in a technical leadership or management role
- B.S. or M.S. in Electrical or Comput