Job DescriptionWe are seeking an experienced, highly motivated and high-caliber individual with below expertise. Does this sound like a good role for you?
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- Staff RTL Design Engineer (R&D; Engineering N
- )Location: Bangalor N
- eExperience: 7yrs to 15yr N
- sBSEE/MSEE in Electrical Engineering, Computer Engineering, or a related field N
- .7 years of hands-on experience in RTL design and verification N
- .Proficiency in Verilog, RTL Coding, Spyglass, industry-standard quality tools (Lint, CDC, RDC, Synthesis) ,TCL scripting, and Formal Verification methodologies N
- .Knowledge of DFT, digital, analog, and mixed-signal IP/circuit design (a plus) N
- .Experience working in Unix/Linux environments N
- .Solid debugging and problem-solving skills, especially in complex chip design environments N
- .Familiarity with 3D-ICstandards and semiconductor verification best practices (desirable) N
- .Responsibilitiesn
- :Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects N
- .Developing comprehensive test cases to ensure robust product functionality and performance N
- .Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis N
- .Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies N
- .Contributing to the improvement of verification methodologies and automation flows N
- .Documenting design specifications, verification plans, and results to ensure transparency and repeatability N
- .Participating in code reviews and technical discussions to drive innovation and continuous improvement N
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n Please share your updated CV with
[email protected] or refer those who would like to explore this opportunit
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- y. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, nati
📌 Senior Staff Rtl Design Engineers (Karnataka)
🏢 Synopsys
📍 Karnataka